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INTEGRATED CIRCUITS
DATA SHEET
SAA7124; SAA7125 Digital Video Encoder (ECO-DENC)
Preliminary specification File under Integrated Circuits, IC22 1996 Nov 07
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
FEATURES * Monolithic CMOS 5 V device * Digital PAL/NTSC encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. "(CCIR 656)" * Four DACs for CVBS (10-bit resolution), RGB (9-bit resolution) operating at 27 MHz; RGB sync on CVBS * Optionally 2 times CVBS and Y, C (all 10-bit resolution) available simultaneously * Closed captioning encoding * On-chip YUV to RGB dematrix optionally to be by-passed for Cr, Y, Cb output on RGB DACs * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase, via input pins or auxiliary codes at MP data port * Programmable horizontal sync output phase * Internal 100/75 Colour Bar Generator (CBG) * Macrovision Pay-per-View copy protection system as option, also partly used for RGB output. This applies to SAA7124 only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information ORDERING INFORMATION TYPE NUMBER SAA7124WP; SAA7125WP SAA7124HZ; SAA7125HZ SAA7124H; SAA7125H Note 1. LQFP64 package for V1 devices only. PACKAGE(1) NAME PLCC84 LQFP64 QFP80 DESCRIPTION plastic leaded chip carrier; 84 leads
SAA7124; SAA7125
* Controlled rise and fall times of output syncs and blanking * Down-mode of DACs * LQFP64 (V1 devices only), QFP80 or PLCC84 package. GENERAL DESCRIPTION The SAA7124; SAA7125 encodes digital YUV video data to an NTSC or PAL CVBS plus RGB or alternatively to S-Video and CVBS output. Optionally, the YUV to RGB dematrix can be by-passed providing the digital-to-analog converted Cb, Y, Cr signals instead of RGB. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs).
VERSION SOT189-2 SOT314-2 SOT318-3
plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm plastic quad flat package; 80 leads (lead length 2.35 mm); body 14 x 20 x 2.8 mm
1996 Nov 07
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILE DLE Tamb analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C, CVBS and RGB without load - (peak-to-peak value) load resistance LF integral linearity error LF differential linearity error operating ambient temperature 80 - - 0 PARAMETER
SAA7124; SAA7125
MIN. 4.75 4.75 - -
TYP. 5.0 5.0 tbf tbf 2.0 - - - -
MAX. 5.25 5.25 60 100 - - 4 1 +70
UNIT V V mA mA V LSB LSB C
TTL compatible
1996 Nov 07
3
full pagewidth
(5)
1996 Nov 07
RTCI CDIR 50 35 36 46 54, 57, 60, 64, 74 48 45 44 37 XTALI RCV1 VDDDO XTALO RCV2 LLC VDDA1 to VDDA5 83 4 SYNC CLOCK 53, 75 clock and timing 8 I2C-bus control 73 67 D 62 8 8 internal control bus MODE I2C-bus control 59 56 65 61 Y RGB PROCESSOR A 58 55 I2C-bus control Y ENCODER C OUTPUT INTERFACE Y CVBS(1) VSSA1 res res res res RED(2) GREEN(3) BLUE(4) 2 VrefH1 VrefH2 I2C-bus control
BLOCK DIAGRAM
RESET SDA SCL SA
Philips Semiconductors
1
84
I2C-BUS INTERFACE
8
25 to 28, 31 to 34 CbCr
Digital Video Encoder (ECO-DENC)
MP7 to MP0
8
DATA MANAGER
I2C-bus control 8 I2C-bus control I2C-bus control
4
CbCr 5, 14, 22, 29, 38, 41, 49, 80, 82 78 SP AP 77 n.c. 2, 16 to 21, 23, 40, 43, 47, 66, 70, 72 69, 71 2 res to 52, 76 2 VrefL1 VrefL2
SAA7124 SAA7125
3, 15, 24, 30, 39, 42, 51, 79, 81
63, 68
MGG550
VSSD1
VDDD1
to
CUR1 CUR2
VSSD9
VDDD9
(1) (2) (3) (4) (5)
Alternatively Y or CVBS. Alternatively CHROMA or Cr. Alternatively CVBS or Yin. Alternatively CVBS or Cb. V1 devices only.
SAA7124; SAA7125
Preliminary specification
Fig.1 Block diagram; PLCC84.
full pagewidth
1996 Nov 07
RTCI CDIR 31 19 20 28 27 29 26 34, 36, 38, 41, 46 21 XTALI RCV1 VDDDO XTALO RCV2 LLC VDDA1 to VDDA5 55 59 SYNC CLOCK 33, 47 clock and timing 8 I2C-bus control Y ENCODER C D I2C-bus control 8 internal control bus MODE 8 I2C-bus control 42, 43 2 OUTPUT INTERFACE 45 Y CVBS(1) VSSA2 2 VrefH1 VrefH2 I2C-bus control
RESET SDA SCL SA
Philips Semiconductors
57
56
I2C-BUS INTERFACE
8
9 to 12, 15 to 18 CbCr
Digital Video Encoder (ECO-DENC)
MP7 to MP0
8
DATA MANAGER
I2C-bus control 8 I2C-bus control I2C-bus control
5
Y RGB PROCESSOR CbCr 5, 7, 13, 22, 24, 30, 52, 54, 60 50 SP AP 49 2 VDDD1 to VDDD9 VrefL1 VrefL2
39 A 37 35
SAA7124 SAA7125
RED(2) GREEN(3) BLUE(4)
6, 8, 14, 23, 25, 51, 53, 58
32, 48 2
40, 44
MGG551
VSSD1
to
CUR1 CUR2
VSSD8
(1) (2) (3) (4)
Alternatively Y or CVBS. Alternatively CHROMA or Cr. Alternatively CVBS or Yin. Alternatively CVBS or Cb.
SAA7124; SAA7125
Preliminary specification
Fig.2 Block diagram; TQFP64, V1 devices only.
agewidth
(5)
1996 Nov 07
RTCI CDIR 38 25 26 34 36 33 32 54, 57, 60, 64, 74 27 XTALI RCV1 VDDDO XTALO RCV2 LLC VDDA1 to VDDA5 71 75 SYNC CLOCK 53, 75 clock and timing 8 control 61 55 D 54 8 8 internal control bus MODE I2C-bus control 51 48 45 50 Y RGB PROCESSOR A 47 44 I2C-bus control I2C-bus Y ENCODER C OUTPUT INTERFACE CVBS(1) VSSA1 res res res res RED(2) GREEN(3) BLUE(4) Y 2 VrefH1 VrefH2 I2C-bus control
RESET SDA SCL SA
Philips Semiconductors
73
72
I2C-BUS INTERFACE
8
15 to 18, 21 to 24 CbCr
Digital Video Encoder (ECO-DENC)
MP7 to MP0
8
DATA MANAGER
I2C-bus control 8 I2C-bus control I2C-bus control
6
CbCr 5, 13, 19, 28, 30, 37, 68, 70, 76 7 to 12, 35, 40 58, 60 66 SP AP 65 n.c. VDDD1 to VDDD9 res 57, 59 2 VrefL1 VrefL2
SAA7124 SAA7125
6, 14, 20, 29, 31, 39, 67, 69, 74
41, 64 2
52, 56
MGG552
VSSD1
to
CUR1 CUR2
VSSD9
(1) (2) (3) (4) (5)
Alternatively Y or CVBS. Alternatively CHROMA or Cr. Alternatively CVBS or Yin. Alternatively CVBS or Cb. V1 devices only.
SAA7124; SAA7125
Preliminary specification
Fig.3 Block diagram; QFP80.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
PINNING PIN SYMBOL RESET TYPE PLCC84 LQFP64 I 1 57 QFP80 73
SAA7124; SAA7125
DESCRIPTION Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. The I2C-bus receiver waits for the START condition. not connected digital ground 1 The I2C-bus slave address select input pin. LOW: slave address = 88H, HIGH = 8CH. digital supply voltage 1
n.c. VSSD1 SA VDDD1 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 VDDD2 VSSD2 n.c. n.c. n.c. n.c. n.c. n.c. VDDD3 n.c. VSSD3 MP7 MP6 MP5 MP4 VDDD4 VSSD4 MP3 MP2 MP1 MP0 RCV1
- I I I O O O O O O O O I I - - - - - - I - I I I I I I I I I I I I/O
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
- 6 59 5 61 62 63 64 1 2 3 4 7 8 - - - - - - 13 - 14 9 10 11 12 22 23 15 16 17 18 19
- 6 75 5 77 78 79 80 1 2 3 4 13 14 7 8 9 10 11 12 19 - 20 15 16 17 18 28 29 21 22 23 24 25
Test pin outputs. Leave open for normal operation.
digital supply voltage 2 digital ground 2
not connected
digital supply voltage 3 not connected digital ground 3 Upper 4 bits of MPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data. digital supply voltage 4 digital ground 4 Lower 4 bits of MPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data. Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
1996 Nov 07
7
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
PIN SYMBOL RCV2 RTCI TYPE PLCC84 LQFP64 I/O I 36 37 20 21 QFP80 26 27 Raster Control 2 for video port. This pin provides an HS pulse of programmable length or receives an HS pulse. Real Time Control input. If the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality. digital supply voltage 5 digital ground 5 not connected digital supply voltage 6 digital ground 6 not connected Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground. Crystal oscillator output (to crystal). digital supply voltage for the internal oscillator; note 1 not connected Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O direction is set by the CDIR pin. digital supply voltage 7 Clock direction. If CDIR input is HIGH, the circuit receives a clock signal, otherwise if CDIR is LOW, LLC is generated by the internal crystal oscillator. digital ground 7 Lower reference voltage 1 input for DACs; connect to analog ground. Upper reference voltage 1 input for DACs; connect via 100 nF capacitor to analog ground. Analog supply voltage 1 for DACs. Analog output of the BLUE component. reserved Analog supply voltage 2 for DACs. Analog output of GREEN component. reserved Analog supply voltage 3 for DACs. Analog output of RED component. reserved Current input 1 for RGB amplifiers; connect via 15 k resistor to VDDA. Analog supply voltage 4 for DACs. reserved not connected 8 DESCRIPTION
VDDD5 VSSD5 n.c. VDDD6 VSSD6 n.c. XTALI XTALO VDDDO n.c. LLC VDDD7 CDIR
I I - I I - I O I - I/O I I
38 39 40 41 42 43 44 45 46 47 48 49 50
24 25 - 30 51 - 26 27 28 - 29 52 31
30 31 35 37 39 40 32 33 34 - 36 68 38
VSSD7 VrefL1 VrefH1 VDDA1 BLUE res VDDA2 GREEN res VDDA3 RED res CUR1 VDDA4 res n.c. 1996 Nov 07
I I I I O I I O I I O I I I I -
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
53 32 33 34 35 - 36 37 - 38 39 - 40 41 - -
67 41 42 43 44 45 46 47 48 49 50 51 52 53 54 -
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
PIN SYMBOL VSSA1 VSSA2 CUR2 res n.c. res n.c. CVBS VDDA5 VrefH2 VrefL2 AP SP VSSD8 VDDD8 VSSD9 VDDD9 SCL SDA Note 1. V1 devices only. TYPE PLCC84 LQFP64 I I I O - O - O I I I I I I I I I I I/O 67 - 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 42 43 44 - - - - 45 46 47 48 49 50 58 54 - 60 55 56 QFP80 55 - 56 57 58 59 60 61 62 63 64 65 66 69 70 74 76 71 72 Analog ground 1 for the DACs. Analog ground 2 for the DACs. Current input 2 for RGB amplifiers; connect via 15 k resistor to VDDA. reserved not connected reserved not connected Analog output of the CVBS signal. Analog supply voltage 5 for DACs. Upper reference voltage 2 input for DACs; connect via 100 nF capacitor to analog ground. Lower reference voltage 2 input for DACs; connect to analog ground. Test pin. Connected to digital ground for normal operation. Test pin. Connected to digital ground for normal operation. digital ground 8 digital supply voltage 8 digital ground 9 digital supply voltage 9 I2C-bus serial clock input. I2C-bus serial data input/output. DESCRIPTION
1996 Nov 07
9
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
handbook, full pagewidth
VDDD1
VDDD9
VDDD8
RESET
VSSD1
VSSD9
VSSD8
11
10
84
83
82
81
80
79
78
77
76
75 74 VDDA5 73 CVBS 72 n.c. 71 res 70 n.c. 69 res 68 CUR2 67 VSSA1 66 n.c. 65 res 64 VDDA4 63 CUR1 62 res 61 RED 60 VDDA3 59 res 58 GREEN 57 VDDA2 56 res 55 BLUE 54 VDDA1 Vref H1 53
9
8
7
6
5
4
3
2
TP7 12 TP8 13 VDDD2 14 VSSD2 15 n.c. 16 n.c. 17 n.c. 18 n.c. 19 n.c. 20 n.c. 21 VDDD3 22 n.c. 23 VSSD3 24 MP7 25 MP6 26 MP5 27 MP4 28 VDDD4 29 VSSD4 30 MP3 31 MP2 32 MP1 33 MP0 34 RCV1 35 RCV2 36 RTCI 37 VDDD5 38 VSSD5 39 n.c. 40 VDDD6 41 VSSD6 42 n.c. 43 XTALI 44 XTALO 45 VDDDO(1) 46 n.c. 47 LLC 48 VDDD7 49 CDIR 50 VSSD7 51 VrefL1 52
SAA7124 SAA7125
1
VrefH2
VrefL2
SDA
SCL
TP6
TP5
TP4
TP3
TP2
TP1
n.c.
SA
SP
AP
MGG548
(1) V1 devices only.
Fig.4 Pin configuration; PLCC84.
1996 Nov 07
10
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
60 VDDD9
54 VDDD8
52 VDDD7
57 RESET
58 VSSD8
handbook, full pagewidth
53 VSSD7
56 SDA
55 SCL
63 TP3
64 TP4
62 TP2
61 TP1
51 VSSD6
49 AP 48 VrefL2 47 VrefH2 46 VDDA5 45 CVBS 44 CUR2 43 VSSA2 42 VSSA1 41 VDDA4 40 CUR1 39 RED 38 VDDA3 37 GREEN 36 VDDA2 35 BLUE 34 VDDA1 33 VrefH1 VrefL1 32
59 SA
TP5 TP6 TP7 TP8 VDDD1 VSSD1 VDDD2 VSSD2 MP7 MP6 MP5 MP4 VDDD3 VSSD3 MP3 MP2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 VDDD6 30 MP1 17 MP0 18 RCV1 19 31 CDIR
SAA7124 SAA7125
VDDD5
RCV2
RTCI
VSSD5
VSSD4
VDDD4
XTALI
XTALO
VDDDO
LLC
50 SP
MGG547
Fig.5 Pin configuration; LQFP64 (V1 devices only).
1996 Nov 07
11
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
76 VDDD9
70 VDDD8
68 VDDD7
73 RESET
74 VSSD9
69 VSSD8
handbook, full pagewidth
67 VSSD7
72 SDA
77 TP1
80 TP4
79 TP3
78 TP2
75 SA
71 SCL
66 SP
65 AP
TP5 TP6 TP7 TP8 VDDD1 VSSD1 n.c. n.c. n.c.
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53
VrefL2 VrefH2 VDDA5 CVBS n.c. res n.c. res CUR2 VSSA1 res VDDA4 CUR1 res RED VDDA3 res GREEN VDDA2 res BLUE VDDA1 VrefH1 VrefL1
n.c. 10 n.c. 11 n.c. 12 VDDD2 13 VSSD2 14 MP7 15 MP6 16 MP5 17 MP4 18 VDDD3 19 VSSD3 20 MP3 21 MP2 22 MP1 23 MP0 24 RCV1 25 RCV2 26 RTCI 27 VDDD4 28 VSSD4 29 VDDD5 30 VSSD5 31 XTALI 32 XTALO 33 34 n.c. 35 LLC 36 VDDD6 37 CDIR 38 VSSD6 39 n.c. 40
SAA7124 SAA7125
52 51 50 49 48 47 46 45 44 43 42 41
(1)
(1) V1 devices only.
Fig.6 Pin configuration; QFP80.
1996 Nov 07
12
VDDDO
MGG549
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
FUNCTIONAL DESCRIPTION The digital video encoder (ECO-DENC) encodes digital luminance and colour difference signals into analog CVBS and simultaneously RGB signals. NTSC-M, PAL B/G standards and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. Optionally, the input Y, Cb and Cr data, digital-to-analog converted, is available at the analog RGB outputs. For applications that do not require RGB output, the device can be configured in such a way that S-Video and twice CVBS is available (Y at CVBS-DAC, C at R-DAC, and CVBS at G-DAC and B-DAC). The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "CCIR 624". For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. For total filter transfer characteristics see Figs 7, 8, 9, 10, 11 and 12. The DACs for Y, C, and CVBS are realized with full 10-bit resolution, DACs for RGB with 9-bit resolution. The MPEG port (MP) accepts 8 line multiplexed Cb, Y, Cr data. The 8-bit multiplexed Cb-Y-Cr formats are "CCIR 656" (D1 format) compatible, but auxiliary codes such as SAV and EAV are decoded optionally for trigger purposes. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to ECO-DENC. Via the RTCI pin, connected to RTCO of a decoder, information concerning actual subcarrier, PAL-ID, and if connected to SAA7111, definite subcarrier phase can be inserted. The ECO-DENC synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock.
SAA7124; SAA7125
The encoder can be configured as slave with respect to RCV trigger inputs or auxiliary "CCIR 656" codes, or can be master to output horizontal and vertical trigger pulses. The IC also contains Closed Caption and Extended Data Services Encoding (Line 21), and supports anti-taping signal generation in accordance with Macrovision. A number of possibilities are provided for setting different video parameters such as: Black and blanking level control Colour subcarrier frequency Variable burst amplitude etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and registers 6BH and 6EH to 00H. All other control registers are not influenced by a reset. Data manager In the data manager, real time arbitration on the data stream to be encoded is performed. Optionally, the device can operate as a 100/75 colour bar test pattern generator without need for an external data source. Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, and blanking level, programmable also in a certain range to allow for manipulations with Macrovision anti-taping, additional insertion of AGC super-white pulses, programmable in height, is supported. In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 9 and 10.
1996 Nov 07
13
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. For transfer characteristics of the chrominance interpolation filter see Figs 7 and 8. The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. ANTI-TAPING (SAA7124 ONLY) For more information contact your nearest Philips Semiconductors sales office. RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, Cb and Cr signals are de-matrixed, 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. For transfer curves of luminance and colour difference components of RGB see Figs 11 and 12. Output interface/DACs
SAA7124; SAA7125
In the output interface encoded both Y and C signals are converted from digital-to-analog in 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. RED, GREEN and BLUE signals (optionally Cr, Y, Cb) are also converted from digital-to-analog, each providing a 9-bit resolution. All output occurs with the same processing delay. Absolute amplitudes at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. Depending on control bits YC_EN and DEMOFF, different signal combinations are available at DACs #1 to #4. YC_EN = DEMOFF = LOW is the default configuration after reset. Table 1 YC_EN 0 0 1 1 Control of DAC signals DEMOFF 0 1 0 1 DAC1 CVBS CVBS VBS VBS DAC2 R Cr C C DAC3 G Y CVBS CVBS DAC4 B Cb CVBS CVBS
Outputs of the DACs can be set together in two groups (#1 and #2 by DOWNB, #3 and #4 by DOWNA) via software control to minimum output voltage for either purpose. Synchronization Synchronization of the ECO-DENC is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port (or equivalently as frame synchronization from "CCIR 656" data stream). The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not to be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin (or a horizontal synchronization from "CCIR 656" data stream). Timing and trigger behaviour can also be influenced for RCV2.
1996 Nov 07
14
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
If there are missing pulses at RCV1 and/or RCV2, the time base of ECO-DENC runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (with the incorrect phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. Alternatively, the device can be triggered by auxiliary codes in a "CCIR 656" data stream at the MP port. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output: * A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or; * An ODD/EVEN signal which is LOW in odd fields, or; * A field sequence signal (FSEQ) which is HIGH in the first of 4, 8 fields respectively. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The polarity of both RCV1 and RCV2 is selectable by software control. Field length is in accordance with to 50 Hz or 60 Hz standards, including non-interlaced options; start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line, If the standard blanking option SBLBN is not set. I2C-bus interface
SAA7124; SAA7125
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses are selected: 88H: LOW at pin SA 8CH: HIGH at pin SA. Input levels and formats ECO-DENC expects digital Y, Cb, Cr data with levels (digital codes) in accordance with "CCIR 601". For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. For RGB (or Y, Cb and Cr) outputs fixed amplification in accordance with "CCIR 601" is provided. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. TRANSFORMATION R = Y + 1.3707 x (Cr - 128) G = Y - 0.3365 x (Cb - 128) - 0.6982 x (Cr - 128) B = Y + 1.7324 x (Cb - 128). Representation of R, G and B at the output is 9 bits at 27 MHz.
Table 2
8-bit multiplexed format (similar to "CCIR 656") BITS TIME 0 1 Y0 0 0 2 Cr0 1 2 Y1 4 Cb2 2 2 5 Y2 6 Cr2 3 7 Y3
Sample Luminance pixel number Colour pixel number
Cb0
1996 Nov 07
15
Bit allocation map
Table 3 DATA BYTE(1) D7 0 0 CBENB 0 0 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 0 0 DOWNB RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 SRCV11 HTRIG7 HTRIG10 SBLBN L21E16 SRCV10 HTRIG6 HTRIG9 0 L21E06 L21O16 L21O06 FSC30 FSC29 L21O05 L21O15 L21E05 L21E15 TRCV2 HTRIG5 HTRIG8 PHRES1 FSC22 FSC21 FSC14 FSC13 FSC06 FSC05 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 ORCV1 HTRIG4 VTRIG4 PHRES0 BSTA6 BSTA5 BSTA4 DOWNA INPI YGS 0 0 0 0 0 BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 PRCV1 HTRIG3 VTRIG3 0 0 BLNVB5 BLNVB4 BLNVB3 DECTYP BLNNL5 BLNNL4 BLNNL3 0 BLCKL5 BLCKL4 BLCKL3 GAINV6 GAINV5 GAINV4 GAINV3 GAINV2 BLCKL2 BLNNL2 BLNVB2 0 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 CBLF HTRIG2 VTRIG2 0 GAINU6 GAINU5 GAINU4 GAINU3 GAINU2 CHPS6 CHPS5 CHPS4 CHPS3 CHPS2 0 0 0 0 0 0 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1 0 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 ORCV2 HTRIG1 VTRIG1 FLC1 0 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0 0 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 PRCV2 HTRIG0 VTRIG0 FLCO 0 0 0 0 0 0 0 YC_EN SYMP DEMOFF 0 Y2C UV2C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
1996 Nov 07
Slave receiver (slave address 88H or 8CH)
REGISTER FUNCTION
SUB ADDRESS
Philips Semiconductors
Null
00
Null
39
I/O port control
3A
Null
42
Null
59
Chrominance phase
5A
Gain U
5B
Gain V
5C
Digital Video Encoder (ECO-DENC)
Gain U MSB, black level
5D
5E
16
Gain V MSB, blanking level, decoder type
Blanking level VBI
5F
Null
60
Standard control
61
RTC enable burst amplitude
62
Subcarrier 0
63
Subcarrier 1
64
Subcarrier 2
65
Subcarrier 3
66
Line 21 odd 0
67
Line 21 odd 1
68
Line 21 even 0
69
Line 21 even 1
6A
RCV port control
6B
Trigger control
6C
SAA7124; SAA7125
Trigger control
6D
Preliminary specification
Multi control
6E
DATA BYTE(1) D7 CCEN1 RCV2S7 RCV2E7 0 0 0 0 0 0 0 0 FAL7 LAL7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAL8 0 FAL8 0 0 0 0 0 LAL6 LAL5 LAL4 LAL3 LAL2 FAL6 FAL5 FAL4 FAL3 FAL2 0 0 0 0 0 0 0 0 0 0 0 0 FAL1 LAL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAL0 LAL0 0 0 0 0 0 0 0 0 0 0 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 RCV2S9 RCV2S8 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2E1 RCV2E0 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2S1 RCV2S0 CCEN0 0 SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0 D6 D5 D4 D3 D2 D1 D0
REGISTER FUNCTION
SUB ADDRESS
1996 Nov 07
Closed caption
6F
RCV2 output start
70
RCV2 output end
71
Philips Semiconductors
MSBs RCV2 output
72
Null
73
Null
74
Null
75
Null
76
Null
77
Null
78
Null
79
First active line
7A
Digital Video Encoder (ECO-DENC)
Last active line
7B
MSBs vertical
7C
17
Null
7D
Null
7E
Null
7F
Note
1. All bits marked 0 must be programmed to zero.
SAA7124; SAA7125
Preliminary specification
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
I2C-bus format Table 4 S Table 5 I2C-bus address; see Table 5 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
SAA7124; SAA7125
--------
DATA n
ACK
P
Explanation of Table 4 PART DESCRIPTION START condition 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S Slave address ACK Subaddress (note 2) DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 6 DATA BYTE UV2C Y2C DEMOFF SYMP YC_EN CBENB Subaddress 3A LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 0 1 Cb, Cr data are two's complement. Cb, Cr data are straight binary. Default after reset. Y data is two's complement. Y data is straight binary. Default after reset. Y, Cb and Cr for RGB dematrix is active. Default after reset. Y, Cb and Cr for RGB dematrix is bypassed. Horizontal and vertical trigger is taken from RCV2 and RCV1 respectively. Default after reset. Horizontal and vertical trigger is decoded out of "CCIR 656" compatible data at MP port. Output of CVBS and RGB signals. Default after reset. Output of Y, C, and CVBS, CVBS signals. Data from input ports is encoded. Default after reset. Colour bar with fixed colours is encoded. The LUTs are read in upward order from index 0 to index 7. DESCRIPTION
1996 Nov 07
18
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 7 Subaddress 5A DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees Subaddress 5B and 5D DESCRIPTION CONDITIONS VALUE tbf tbf tbf tbf
SAA7124; SAA7125
DATA BYTE CHPS
RESULT PAL-B/G and data from input ports PAL-B/G and data from look-up table NTSC-M and data from input ports NTSC-M and data from look-up table
Table 8
DATA BYTE GAINU
REMARKS output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
variable gain for Cb signal; white-to-black = 92.5 IRE(1) input representation GAINU = 0 accordance with GAINU = 118 (76H) "CCIR 601" white-to-black = 100 IRE(2) GAINU = 0 GAINU = 125 (7DH)
Notes 1. GAINU = -2.17 x nominal to +2.16 x nominal. 2. GAINU = -2.05 x nominal to +2.04 x nominal. Table 9 Subaddress 5C and 5E DESCRIPTION variable gain for Cr signal; input representation accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 GAINV = 0 GAINV = 175 (AFH) Notes 1. GAINV = -1.55 x nominal to +1.55 x nominal. 2. GAINV = -1.46 x nominal to +1.46 x nominal. IRE(2) output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal IRE(1) output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal REMARKS
DATA BYTE GAINV
1996 Nov 07
19
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 10 Subaddress 5D DATA BYTE BLCKL DESCRIPTION CONDITIONS
SAA7124; SAA7125
REMARKS output black level = 24 IRE output black level = 49 IRE output black level = 24 IRE output black level = 50 IRE
variable black level; input white-to-sync = 140 IRE(1) representation accordance BLCKL = 0 with "CCIR 601" BLCKL = 63 (3FH) white-to-sync = 143 BLCKL = 0 BLCKL = 63 (3FH) IRE(2)
Notes 1. Output black level/IRE = BLCKL x 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL x 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. Table 11 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE(1) BLNNL = 0 BLNNL = 63 (3FH) white-to-sync = 143 IRE(2) BLNNL = 0 BLNNL = 63 (3FH) DECTYP RTCI logic 0 logic 1 Notes 1. Output black level/IRE = BLNNL x 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL x 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. Table 12 Subaddress 5F DATA BYTE BLNVB DESCRIPTION variable blanking level during vertical blanking interval is typically identical to value of BLNNL output blanking level = 17 IRE output blanking level = 43 IRE real time control input from SAA7151B real time control input from SAA7111 output blanking level = 17 IRE output blanking level = 42 IRE REMARKS
1996 Nov 07
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 13 Subaddress 61 DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 1 YGS INPI DOWNA 0 1 0 1 0 1 DOWNB 0 1 858 total pixel clocks per line NTSC encoding (non-alternating V component) DESCRIPTION 864 total pixel clocks per line; default after reset
SAA7124; SAA7125
PAL encoding (alternating V component); default after reset enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 7 and 8) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 7 and 8); default after reset luminance gain for white - black 100 IRE; default after reset luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal DACs for G and B (Y and Cb or CVBS and CVBS) in normal operational mode; default after reset DACs for G and B (Y and Cb or CVBS and CVBS) forced to lowest output voltage DACs for CVBS and R (CVBS and Cr or VBS and C) in normal operational mode; default after reset DACs for CVBS and R (CVBS and Cr or VBS and C) forced to lowest output voltage
Table 14 Subaddress 62A DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 x nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 x nominal Table 15 Subaddress 62B DATA BYTE RTCE LOGIC LEVEL 0 1 DESCRIPTION no real time control of generated subcarrier frequency real time control of generated subcarrier frequency through SAA7151B or SAA7111 (timing see Fig.15) recommended value: BSTA = 75 (4BH) recommended value: BSTA = 106 (6AH) recommended value: BSTA = 72 (48H) REMARKS recommended value: BSTA = 102 (66H
1996 Nov 07
21
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 16 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS f fsc 32 FSC = round ------- x 2 f llc see note 1
SAA7124; SAA7125
REMARKS FSC3 = most significant byte FSC0 = least significant byte
FSC0 to FSC3 ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) Note 1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). Table 17 Subaddress 67 to 6A DATA BYTE L21O0 L21O1 L21E0 L21E1 DESCRIPTION first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field REMARK LSB of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format
1996 Nov 07
22
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 18 Subaddress 6B DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION
SAA7124; SAA7125
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively pin RCV2 is switched to input; default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default after reset if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = HIGH); default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a `Composite-Blanking-Not' signal, this is a reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking Interval, which is defined by FAL and LAL if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = HIGH) and as an internal blanking signal
PRCV1
0 1
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input pin RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of "CCIR 656" input (at bit SYMP = HIGH); default after reset horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) defines signal type on pin RCV1; see Table 19
ORCV1 TRCV2
0 1 0 1
SRCV1
-
Table 19 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 1 SRCV10 0 1 0 1 VS FS FSEQ not applicable VS FS FSEQ not applicable vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) - AS INPUT FUNCTION
1996 Nov 07
23
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 20 Subaddress 6C and 6D DATA BYTE HTRIG DESCRIPTION
SAA7124; SAA7125
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input (or to decoded "CCIR 656" data) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = tbfH (tbfH)
Table 21 Subaddress 6D DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input (or to decoded "CCIR 656" data) increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) Table 22 Subaddress 6E DATA BYTE SBLBN LOGIC LEVEL 0 1 PHRES FLC - - DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset vertical blanking is forced in accordance with "CCIR 624" (50 Hz) or "RS170A" (60 Hz) selects the phase reset mode of the colour subcarrier generator; see Table 23 field length control; see Table 24
Table 23 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset reset every two lines reset every eight fields reset every four fields
Table 24 Logic levels and function of FLC DATA BYTE FUNCTION FLC1 0 0 1 1 FLC0 0 1 0 1 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
1996 Nov 07
24
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 25 Subaddress 6F DATA BYTE CCEN SCCLN DESCRIPTION enables individual Line 21 encoding; see Table 26
SAA7124; SAA7125
selects the actual line, where closed caption or extended data are encoded line = (SCCLN + 4) for M-systems line = (SCCLN + 1) for other systems
Table 26 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
Table 27 Subaddress 70 to 72 DATA BYTE RCV2S start of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = tbfH (tbfH) RCV2E end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = tbfH (tbfH) Table 28 Subaddress 7A to 7C DATA BYTE FAL LAL DESCRIPTION first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse SUBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. DESCRIPTION
1996 Nov 07
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Slave Transmitter Table 29 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte Table 30 No subaddress DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ O_E 1 0 1 0 DESCRIPTION DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3
SAA7124; SAA7125
D2 0
D1 FSEQ
D0 O_E
CCRDO CCRDE
Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current Version is 100 binary. Closed caption bytes of the odd field have been encoded. The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data has been encoded. Closed caption bytes of the even field have been encoded. The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data has been encoded. During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields. Not first field of a sequence. During even field. During odd field.
1996 Nov 07
26
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(1) SCBW = 1. (2) SCBW = 0.
Fig.7 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.8 Chrominance transfer characteristic 2.
1996 Nov 07
27
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
handbook, full pagewidth 6
MGG556
Gv
(dB)
0
(1)
-6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) (1) Total luminance of Y and CVBS. 14
Fig.9 Luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) Detailed luminance of Y and CVBS.
Fig.10 Luminance transfer characteristic 2.
1996 Nov 07
28
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB708
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.11 Luminance transfer characteristic in RGB.
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB706
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.12 Colour difference transfer characteristic in RGB.
1996 Nov 07
29
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
CHARACTERISTICS VDDD = 4.75 to 5.25 V; Tamb = 0 to +70 C; unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA IDDD Inputs VIL VIH LOW level input voltage (except SDA, SCL, AP, SP and XTALI) HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) HIGH level input voltage (LLC) ILI Ci input leakage current input capacitance clocks data I/Os at high impedance Outputs VOL VOH LOW level output voltage (except SDA and XTALO) HIGH level output voltage (except LLC, SDA, and XTALO) HIGH level output voltage (LLC) I2C-bus; SDA and SCL VIL VIH Ii VOL Io TLLC tr tf tSU;DAT tHD;DAT LOW level input voltage HIGH level input voltage input current LOW level output voltage (SDA) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge note 2 note 2 note 2 0 analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 PARAMETER CONDITIONS
SAA7124; SAA7125
MIN.
MAX.
UNIT
4.75 4.75 - - -0.5 2.0 2.4 - - - -
5.25 5.25 60 100
V V mA mA
+0.8 VDDD + 0.5 VDDD + 0.5 1 10 8 8
V V V A pF pF pF
0.6 VDDD + 0.5 VDDD + 0.5
V V V
2.4 2.6 -0.5 3.0 -10 - 3
+1.5 VDDD + 0.5 +10 0.4 -
V V A V mA
Clock timing (LLC) cycle time duty factor tHIGH/TLLC rise time fall time note 3 note 4 note 3 note 3 34 40 - - 41 60 5 6 - - ns % ns ns
Input timing input data set-up time (any other except CDIR, SCL, SDA, RESET, AP and SP) input data hold time (any other except CDIR, SCL, SDA, RESET, AP and SP) 6 3 ns ns
1996 Nov 07
30
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
SYMBOL Crystal oscillator fn f/fn Tamb CL RS C1 C0 CL th td Vo(p-p) Rint RL B ILE DLE Notes
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 5
30 +50
MHz 10-6 C pF fF pF
-50 0 8 - 1.5 - 20% 3.5 - 20%
CRYSTAL SPECIFICATION operating ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 70 - 80 1.5 + 20% 3.5 + 20%
Data and reference signal output timing output load capacitance output hold time output delay time 7.5 4 - 40 - 25 pF ns ns
CHROMA, Y, CVBS and RGB outputs output signal voltage (peak-to-peak value) internal serial resistance output load resistance output signal bandwidth of DACs LF integral linearity error of DACs LF differential linearity error of DACs -3 dB note 6 1.9 18 80 10 - - 2.1 35 - - 4 1 V MHz LSB LSB
1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 k to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
1996 Nov 07
31
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.13 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to 0F2H (110H for 50 Hz) in this example in output mode (RCV2S).
Fig.14 Functional timing.
1996 Nov 07
32
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
handbook, full pagewidth
H/L transition count start LOW 128
13
4 bits reserved HPLL increment
0 21
sequence reserved (2) 5 bits bit (1) reset reserved bit (3) FSCPLL increment (4)
0
RTCI time slot: 0 1
14 19 67 68
not used in SAA7124/25
valid sample
invalid sample
8/LLC
MGG557
(1) Sequence bit: PAL = logic 0 then (R - Y) line normal; PAL = logic 1 then (R - Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems. (3) Only from SAA7111 decoder. (4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.15 RTCI timing.
1996 Nov 07
33
andbook, full pagewidth
1996 Nov 07
+5 V analog 15 k 10 pF +5 V digital 0.1 F VSSD VSSA CUR 63, 68 VDDA2 57 VDDA3 60 VDDA5 74 VDDDO 46 VDDA4 64 VDDA1 54 VrefH 53, 75 XTALO 45
(4)
VSSD 0.1 F 0.1 F 0.1 F 0.1 F VSSA VSSA VSSA
10 H 0.1 F VSSA 0.1 F VSSA
Philips Semiconductors
10 pF
1 nF
(3)
APPLICATION INFORMATION
X1 27.0 MHz
3rd harmonic
XTALI 44
digital inputs and outputs DAC1 35 (1) 73 12 75 CVBS 1.23 V (p-p)(2) VSSA DAC2 35 (1) 61 74 75
Digital Video Encoder (ECO-DENC)
0.1 F
VSSD
VDDD1 5
0.1 F
VSSD
VDDD2 14
34
SAA7124 SAA7125
DAC3 DAC4 3, 15, 24, 30, 39, 42, 51, 79, 81 VSSD1 to VSSD9 VSSA 52, 76 VrefL
0.1 F
VSSD
VDDD3 22
0.1 F
RED 0.7 V (p-p)(2) VSSA 35 (1) 58 74 75 GREEN 0.7 V (p-p)(2) VSSA 35 (1) 55 74 75 67 VSSA1
MGG553
VSSD
VDDD4 29
0.1 F
VSSD
VDDD5 38
0.1 F
VSSD
VDDD6 41
0.1 F
VSSD
VDDD7 49
0.1 F
VSSD
VDDD8 80
0.1 F
VSSD
VDDD9 82
BLUE 0.7 V (p-p)(2) VSSA
+5 V digital
(1) Typical value. (2) For 100100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) V1 devices only.
SAA7124; SAA7125
Preliminary specification
Fig.16 Application environment of the ECO-DENC; PLCC84.
dbook, full pagewidth
1996 Nov 07
+5 V analog 15 k 10 pF VSSA 0.1 F VSSA VSSA VrefH 33, 47 CUR 40, 44 VDDA1 34 VDDA2 36 VDDA3 38 VDDA5 46 0.1 F VSSA 0.1 F VSSA +5 V digital 0.1 F VSSD XTALO 27 VDDDO 28 VDDA4 41 0.1 F 0.1 F VSSA 0.1 F
(3)
VSSD
10 H
Philips Semiconductors
10 pF
1 nF
X1 27.0 MHz
3rd harmonic
XTALI 20
digital inputs and outputs DAC1 35 (1) 45 12 75 CVBS 1.23 V (p-p)(2) VSSA DAC2 35 (1) 39 74 75
0.1 F
Digital Video Encoder (ECO-DENC)
VSSD
VDDD1 5
0.1 F
VSSD
VDDD2 7
35
SAA7124 SAA7125
DAC3 DAC4 6, 8, 14, 23, 25, 51, 53, 58 VSSD1 to VSSD8 VSSA 32, 48 VrefL
0.1 F
VSSD
VDDD3 13
0.1 F
RED 0.7 V (p-p)(2) VSSA 35 (1) 37 74 75 GREEN 0.7 V (p-p)(2) VSSA 35 (1) 35 74 75 42, 43 VSSA1
MGG554
VSSD
VDDD4 22
0.1 F
VSSD
VDDD5 24
0.1 F
VSSD
VDDD6 30
0.1 F
VSSD
VDDD7 52
0.1 F
VSSD
VDDD8 54
0.1 F
VSSD
VDDD9 60
BLUE 0.7 V (p-p)(2) VSSA
+5 V digital
(1) Typical value. (2) For 100100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003.
SAA7124; SAA7125
Preliminary specification
Fig.17 Application environment of the ECO-DENC; LQFP64 (V1 devices only).
dbook, full pagewidth
1996 Nov 07
+5 V analog 15 k 10 pF +5 V digital 0.1 F VSSD VSSA VrefH 42, 63 CUR 52, 56 VDDA1 43 VDDA2 46 VDDA3 49 VDDA5 62 XTALO 33 VDDDO(4) 34 VDDA4 53 VSSA 0.1 F 0.1 F VSSA 0.1 F VSSA VSSA 0.1 F 0.1 F VSSA 0.1 F
(3)
VSSD
10 H
Philips Semiconductors
10 pF
1 nF
X1 27.0 MHz
3rd harmonic
XTALI 32
digital inputs and outputs DAC1 35 (1) 61 12 75 CVBS 1.23 V (p-p)(2) VSSA DAC2 35 (1) 50 74 75
0.1 F
Digital Video Encoder (ECO-DENC)
VSSD
VDDD1 5
0.1 F
VSSD
VDDD2 13
36
SAA7124 SAA7125
DAC3 DAC4 6, 14, 20, 29, 31 39, 67, 69, 74 VSSD1 to VSSD8 VSSA 41, 64 VrefL
0.1 F
VSSD
VDDD3 19
0.1 F
RED 0.7 V (p-p)(2) VSSA 35 (1) 47 74 75 GREEN 0.7 V (p-p)(2) VSSA 35 (1) 44 74 75 55 VSSA1
MGG555
VSSD
VDDD4 28
0.1 F
VSSD
VDDD5 30
0.1 F
VSSD
VDDD6 37
0.1 F
VSSD
VDDD7 68
0.1 F
VSSD
VDDD8 70
0.1 F
VSSD
VDDD9 76
BLUE 0.7 V (p-p)(2) VSSA
+5 V digital
(1) Typical value. (2) For 100100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) V1 devices only.
SAA7124; SAA7125
Preliminary specification
Fig.18 Application environment of the ECO-DENC; QFP80.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
PACKAGE OUTLINES PLCC84: plastic leaded chip carrier; 84 leads
SAA7124; SAA7125
SOT189-2
eD y 74 75 X 54 53 Z E A
eE
bp b1 wM 84 HE A A4 A1 (A 3) k1 Lp detail X 12 e D HD 0 5 scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
1
pin 1 index e
E
k
11 32 ZD
33
vM A B vMB 10 mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
29.41 29.41 28.70 28.70 30.35 30.35 1.22 1.27 29.21 29.21 27.69 27.69 30.10 30.10 1.07
45 o
0.180 inches 0.020 0.01 0.165
1.130 1.130 1.195 1.195 0.048 0.057 0.021 0.032 1.158 1.158 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 1.090 1.090 1.185 1.185 0.042 0.040 0.013 0.026 1.150 1.150
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT189-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1996 Nov 07
37
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L A A2 A1
Q (A 3) Lp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 Q 0.69 0.59 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-01-07 95-12-19
1996 Nov 07
38
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
QFP80: plastic quad flat package; 80 leads (lead length 2.35 mm); body 14 x 20 x 2.8 mm
SOT318-3
c
y X
64 65
41 40 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
wM pin 1 index 80 1 wM D HD ZD B vMB 24 25 bp
e
bp
vMA
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.25 A1 0.30 0.10 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 25.0 24.4 HE 19.0 18.4 L 2.35 Lp 1.4 1.0 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-3 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 95-04-25
1996 Nov 07
39
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC and QFP packages. The choice of heating method may be influenced by larger PLCC or QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering PLCC Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
SAA7124; SAA7125
* The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. QFP Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). METHOD (PLCC AND QFP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Nov 07
40
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7124; SAA7125
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 07
41
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
NOTES
SAA7124; SAA7125
1996 Nov 07
42
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
NOTES
SAA7124; SAA7125
1996 Nov 07
43
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/01/pp44
Date of release: 1996 Nov 07
Document order number:
9397 750 01467

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